1. Technical Field
The present invention relates generally to communication link circuits, and more particularly, to transmitters and/or receivers having selectable complexity and operating voltage levels within signal processing blocks.
2. Description of the Related Art
Interfaces between present-day system devices and also between circuits have increased in operating frequency and complexity. In particular, high speed serial interfaces require data/clock extraction, jitter reduction, phase correction, error correction, error recovery circuits and equalization circuits that can become very complex, depending on the performance requirements of a particular interface. As the above-mentioned circuits become more complex, they have an increasingly large proportion of digital logic and the overall amount of digital logic employed in both receiver and transmitter circuits has increased substantially.
More complex digital receiver and transmitter circuits typically require higher minimum operating voltages, as maximum delay, minimum risetime and similar performance requirements are increased for more complex processing and are met at higher minimum operating voltages, which include power supply voltages and bias voltages that affect power consumption, such as bias or power-plane voltages applied to the substrate or body of a transistor.
Due to limited design resources and the need to satisfy the requirements of multiple interface applications, customers and channel conditions, transmitters and receivers within above-described interfaces are typically designed for the worst-case bit error rates and environmental conditions, leading to relatively complex receivers and high power transmitters and higher operating voltages than are required for every application or channel condition. As a result, it is not always possible to provide a receiver that is not more complex than necessary when a high channel quality is available. Higher complexity generally leads to a higher minimum operating voltage for the signal processing blocks. For example, processing delay associated with a pipelined digital filtering circuit depends on the complexity of the circuit, such as the number of levels of logic gates between latches and the number of latches in the filter circuit. A higher complexity circuit requires faster gates and latches to achieve the same processing delay, which in turn requires a higher minimum operating voltage for the circuit gates and latches. Similar minimum operating voltage determining factors such as phase correction resolution and range are present in other circuits. A higher operating voltage in turn raises both circuit power dissipation and power supply input requirements. Thus, both the complexity of the logic and the operating voltage of the processing circuits depend on the required performance parameters of the interface and the channel conditions connecting interface transceivers.
It is therefore desirable to provide an interface transceiver having reduced power consumption and signal processing supply voltage requirements.